`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/10/17 14:37:18
// Design Name: 
// Module Name: subtractor6
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module subtractor6(
    input rst,        // 重置为0
    input cp,           // 时钟脉冲信号，周期2s
    input clk,
    output reg  [3:0] out, // 当前寄存器的数字
    output reg cout
    );
    always @(posedge cp or negedge rst) begin
        if (!rst) begin
            out <= 0;
        end
        else if (out > 4'b0) begin
            out <= out - 1;
        end
        else out <= 4'b0101;
    end
    always @(posedge clk) begin
        if (out==4'h5) begin
            cout <= 1'b1;            
        end
        else cout <= 1'b0;
    end
endmodule
